FIG. 1 is a plan view illustrating a standard SOI self aligned FET where source S and drain D are formed in an epitaxial layer of silicon formed on the silicon oxide insulating layer. An epitaxial silicon body region underlying the gate G separates the source and drain. As will be appreciated by those skilled in the art, semiconductor devices fabricated with SOI technology have a number of operational characteristics that make them a desirable alternative to devices fabricated with bulk silicon technologies. However, if the body of an SOI transistor device floats (i.e. is not connected to a potential source), the device IV characteristics and threshold voltage may vary with the switching history the device experiences in actual operation. A cure for the floating body problems in SOI transistors is the formation of a contact to the body of the device to allow the body to be connected to a potential source so that the body no longer floats. While provision of a body contact is straightforward in principle, it is not straightforward in practice. The prior art has made a number of proposals for providing a connection to the body of an SOI device.
A prior art SOI transistor with a body contact region labeled "B" is illustrated in FIG. 2. The body contact region is doped with the same polarity as the body of the transistor (and the opposite polarity of the Source and Drain). Prior art "T" shaped devices such as that shown in FIG. 2, while generally satisfactory, have the disadvantage that more than one device cannot share the same rx bed with another "T" device. U.S. Pat. No. 5,405,795, assigned to the assignee of this application, discloses an SOI transistor with a self aligned body contact formed through an extension to the gate.
FIG. 3 is a schematic drawing of an exemplary prior art sense amplifier; i.e., a sense amplifier circuit for a SRAM. The two lines labeled RDBC and RDBT will be pulled apart by the cell during a read operation.
As will be appreciated by those skilled in the art, the differential output generated by the cell on RDBT and RDBC are coupled to the drains of the transistors. When the differential voltage between RDBT and RDBC reaches a threshold value (e.g. about ten percent of the output value), one of transistors (depending on the relative polarity of RDBT and RDBC) turns rapidly on and the other turns rapidly off. The outputs of the amplifier are taken from the drains. As will be appreciated by those skilled in the art, the speed of silicon-on-insulator FETs makes them a potentially attractive technology with which to implement such differential amplifiers. However, if the body potential changes, the threshold voltage can change.
When the signal is received, the amplifier turns on, pulling the RDBC and RDBT lines apart.
The amount of signal required for reliable operation depends on the tolerance which must be allowed for changes in the threshold voltage difference on the parallel connected transistor pairs. Any threshold voltage difference between one pair and the other requires an additional signal on the input lines to guarantee that the lines will be pulled apart in the correct direction.
When such exemplary, critical transistors are built in an SOI technology, the body voltages of the critical transistors will depend on the history of the data read from the cells. As the history is not under the control of the designer, the amplifier must be designed so that it will work with any data pattern. If multiple identical data values are read, a body voltage difference between the transistor pairs will build up over time. This will cause a threshold voltage difference between them which must be compensated for in the design. In the prior art, compensation is provided by increasing the bit line differential before the sense amplifier is turned on. The additional signal requires more time to reach the threshold level, thus reducing the performance of the SRAM. Prior art body contact approaches have not been altogether satisfactory for this application. Another example of a prior art sense amplifier to which the teachings of this invention are applicable is disclosed in U.S. Pat. No. 5,627,484, assigned to the assignee of this application and incorporated herein by reference.